Exemplary embodiments of the present invention relate to a semiconductor technology, and more particularly, to a data output circuit of a semiconductor memory device.
A semiconductor memory device generally includes a data output circuit for outputting internally stored data signals to the outside. Particularly, a data output circuit of a semiconductor memory device applied to a personal computer (PC) may include an On Die Terminal (ODT). The ODT controls a resistance value on the part of a data pad when a semiconductor memory device is integrated with a board so that data signals are transferred without impedance mismatch between the semiconductor memory device and the board. Meanwhile, a data output circuit of a semiconductor memory device used for consumer products such as a set-top box, a navigation system, a digital television (DTV) and the like may not be equipped with an ODT in order to save costs. Hereafter, a data output circuit of a semiconductor memory device without an ODT is described.
FIG. 1 is a circuit diagram illustrating a data output circuit of a conventional semiconductor memory device.
Referring to FIG. 1, the data output circuit 100 includes a pull-up pre-driver 110, a pull-up main driver 120, a pull-down pre-driver 130, a pull-down main driver 140, a pull-up state converter 150, and a pull-down state converter 160. The pull-up pre-driver 110 outputs a pull-up drive control signal /UP in response to a data signal DATA_OUT transferred from a memory cell (not shown). The pull-up main driver 120 pull-up drives a final output terminal DOUT in response to the pull-up drive control signal /UP. The pull-down pre-driver 130 outputs a pull-down drive control signal DN in response to a data signal DATA_OUT transferred from a memory cell (not shown). The pull-down main driver 140 pull-down drives a final output terminal DOUT in response to the pull-down drive control signal DN. The pull-up state converter 150 is coupled with an input terminal of the pull-up pre-driver 110 in parallel and converts the state of the final output terminal DOUT into a high impedance (Hi-Z) state in response to an off signal OUTOFF. The pull-down state converter 160 is coupled with an input terminal of the pull-down pre-driver 130 in parallel and converts the state of the final output terminal DOUT into a high impedance (Hi-Z) state in response to an off bar signal /OUTOFF, which is an inversion of the off signal OUTOFF.
The pull-up pre-driver 110 may include an inverter. For example, the pull-up pre-driver 110 may include a first PMOS transistor P1 and a first NMOS transistor N1. The first PMOS transistor P1 receives the data signal DATA_OUT as a gate input and includes source/drain terminals coupled to a terminal of a power source voltage VDDQ and an output terminal of the pull-up pre-driver 110. The first NMOS transistor N1 receives the data signal DATA_OUT as a gate input and includes source/drain terminals coupled to a terminal of a ground voltage VSSQ and the output terminal of the pull-up pre-driver 110. The pull-up main driver 120 may include a second PMOS transistor P2 which receives the pull-up drive control signal /UP as a gate input and includes source/drain terminals coupled to the terminal of the power source voltage VDDQ and the final output terminal DOUT.
The pull-down pre-driver 130 may include an inverter, just as the pull-up pre-driver 110 does. To be specific, the pull-down pre-driver 130 may include a third PMOS transistor P3 and a second NMOS transistor N2. The third PMOS transistor P3 receives the data signal DATA_OUT as a gate input and includes source/drain terminals coupled to the terminal of the power source voltage VDDQ and an output terminal of the pull-down pre-driver 130. The second NMOS transistor N2 receives the data signal DATA_OUT as a gate input and includes source/drain terminals coupled to the terminal of the ground voltage VSSQ and the output terminal of the pull-down pre-driver 130.
The pull-down main driver 140 may include a third NMOS transistor N3 which receives the pull-down drive control signal DN as a gate input and includes source/drain terminals coupled to the terminal of the ground voltage VSSQ and the final output terminal DOUT.
The pull-up state converter 150 includes a fourth NMOS transistor N4 which receives the off signal OUTOFF as a gate input and includes source/drain terminals coupled to the terminal of the ground voltage VSSQ and the input terminal of the pull-up pre-driver 110. Herein, the off signal OUTOFF is a high active signal for making the state of the final output terminal DOUT into a high impedance (Hi-Z) state after a read operation is finished. The final output terminal DOUT becomes the high impedance (Hi-Z) state after a read operation is finished so as to prevent a conflict between signals that may occur through a data pad DQ.
The pull-down state converter 160 includes a fourth PMOS transistor P4 which receives the off bar signal /OUTOFF as a gate input and includes source/drain terminals coupled to the terminal of the power source voltage VDDQ and the input terminal of the pull-down pre-driver 130.
Hereafter, an operation of the conventional data output circuit 100 having the structure shown in FIG. 1 is described with reference to FIG. 2.
FIG. 2 is a timing diagram illustrating the operation of the data output circuit 100 shown in FIG. 1.
Referring to FIG. 2, since the off signal OUTOFF maintains an enabled state, which is a logic high level state, before a read operation is performed, the pull-up state converter 150 and the pull-down state converter 160 are turned on. Accordingly, a pull-up state conversion signal UP_PRE of a logic low level is inputted into the input terminal of the pull-up pre-driver 110. Therefore, the pull-up main driver 120 receives the pull-up drive control signal /UP of a logic high level and it is turned off. Meanwhile, the input terminal of the pull-down pre-driver 130 receives a pull-down state conversion signal /DN_PRE of a logic high level. Therefore, the pull-down main driver 140 receives the pull-down drive control signal DN of a logic low level and it is turned off. Accordingly, the final output terminal DOUT becomes a high impedance (Hi-Z) state, generating a voltage level which is neither a logic high level nor a logic low level. In short, an external data signal DATA_OUTF outputted through the final output terminal DOUT may have an arbitrary/floating voltage level between the power source voltage VDDQ level and a ground voltage VSSQ level.
As the read operation is performed in this state, the off signal OUTOFF is disabled, that is, the off signal OUTOFF transitions from a logic high level to a logic low level. Of course, the off bar signal /OUTOFF transitions from a logic low level to a logic high level. Then, the pull-up state converter 150 and the pull-down state converter 160 are turned off, and the data signal DATA_OUT begins to enter the input terminals of the pull-up pre-driver 110 and the pull-down pre-driver 130. In other words, the data signal DATA_OUT enters the input terminal of the pull-up pre-driver 110 as the pull-up state conversion signal UP_PRE, and the data signal DATA_OUT enters the input terminal of the pull-down pre-driver 130 as the pull-down state conversion signal /DN_PRE. Accordingly, the pull-up pre-driver 110 outputs the pull-up drive control signal /UP, which is an inversion of the pull-up state conversion signal UP_PRE, and the pull-down pre-driver 130 outputs the pull-down drive control signal DN, which is an inversion of the pull-down state conversion signal /DN_PRE. Therefore, the pull-up main driver 120 pull-up drives the final output terminal DOUT in response to the pull-up drive control signal /UP, and the pull-down main driver 140 pull-down drives the final output terminal DOUT in response to the pull-down drive control signal DN. Thus, the external data signal DATA_OUTF is outputted to the outside through the data pad DQ.
Subsequently, after the read operation is ended, the off signal OUTOFF transitions from a logic low level to a logic high level, and the pull-up state converter 150 and the pull-down state converter 160 are turned on. Then, as described above, since the pull-up main driver 120 and the pull-down main driver 140 are turned off, the state of the final output terminal DOUT returns to the high impedance (Hi-Z) state.
According to the conventional data output circuit 100, when a read operation is not performed, the state of the final output terminal DOUT is converted into the high impedance (Hi-Z) state and thereby conflict between signals which may occur through the data pad DQ may be prevented.
However, the conventional data output circuit 100 has the following concerns.
The high impedance (Hi-Z) state means a third state which is neither a logic high level nor a logic low level, and the final output terminal DOUT may have an arbitrary voltage value between the power source voltage VDDQ level and the ground voltage VSSQ level in the high impedance (Hi-Z) state. In this case, the external data signal DATA_OUTF which begins to be outputted through the final output terminal DOUT when a read operation is initiated may be affected by the arbitrary value. For example, as illustrated in FIG. 2, when the arbitrary value is close to the ground voltage VSSQ level at the moment when the external data signal DATA_OUTF begins to be outputted through the final output terminal DOUT, swing may not be sufficiently performed to the power source voltage VDDQ level. Therefore, the signal integrity (SI) characteristics of the data output circuit 100 may be deteriorated and a yield loss of the semiconductor memory device may occur. However, if the data output circuit 100 includes an ODT, the final output terminal DOUT may not maintain an arbitrary value level but instead maintains a half power source voltage VDDQ/2 level, which corresponds to a level that is half of the power source voltage VDDQ level. Thus, full swing may be performed at the moment when the external data signal DATA_OUTF is outputted. In this case, however, the presence of the ODT may induce a loss of net die.
Meanwhile, to address the concerns of the conventional data output circuit 100, that is, to improve the signal integrity (SI) characteristics of the data output circuit 100, the sizes of the pull-up main driver 120 and the pull-down main driver 140 may be increased. In this case, however, an overshoot and/or undershoot phenomenon may occur in the external data signal DATA_OUTF outputted through the data pad DQ.